This document lists general directions of TPU-MLIR, include principal goals, plans, etc.
Principal goals#
- keep regular sync with mlir from project llvm-project.
- continue maintaining high-quality, well-tested and documented modules.
- support AI machine learning frameworks: ONNX, TFLite, Caffe.
- support various neuron network models, such as resnet, yolo, ssd, bert, etc.
- support various chips, especially SOPHGO TPU, such as BM1684X, BM1684, CV18XX, Athena2, etc.
- follow newest MLIR compiler technology, and put it on this project efficently.
- keep high performance and hign accuraccy, especially for INT8 quantization models.
- support various tools to improve development conveniently and efficiently.
Plans#
development plans【2022-2023】#
| Chip | Product |
|---|---|
| BM1684X | SC7, SE7 |
| BM1684 | SC5, SG6, SE6, SE5, SM5 |
| CV18XX | CV1838, CV1835, CV1826, CV1825, CV1823, CV1821, CV1820, CV1813H, CV1812H, CV1811H, CV1810H, CV1812C, CV1811C |
| Athena2 | on going |